Optimize barrier usage during Cortex-A57 power down

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index e7774974a4df4885f4c4bd0219fa9dd23330e457..c2e11bd93107999b3b33156036a5e29e196bb60f 100644 (file)
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -57,7 +57,7 @@ func cortex_a57_disable_l2_prefetch
        bic     x0, x0, x1
        msr     CPUECTLR_EL1, x0
        isb
-       dsb     sy
+       dsb     ish
        ret
 
        /* ---------------------------------------------